]> granicus.if.org Git - llvm/commit
Merging r341221:
authorTom Stellard <tstellar@redhat.com>
Tue, 13 Nov 2018 05:28:23 +0000 (05:28 +0000)
committerTom Stellard <tstellar@redhat.com>
Tue, 13 Nov 2018 05:28:23 +0000 (05:28 +0000)
commitb7cd010ff5e925f168e6eb7a2687e831073ea5b0
tree26b53d24ed27adb8ffd726dc247ebc50b86966f3
parentaaf6ddfa1c79c9610bc35f208514a516d2cbbd5b
Merging r341221:

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r341221 | atanasyan | 2018-08-31 08:57:17 -0700 (Fri, 31 Aug 2018) | 12 lines

[mips] Fix `mtc1` and `mfc1` definitions for microMIPS R6

The `mtc1` and `mfc1` definitions in the MipsInstrFPU.td have MMRel,
but do not have StdMMR6Rel tags. When these instructions are emitted
for microMIPS R6 targets, `Mips::MipsR62MicroMipsR6` nor
`Mips::Std2MicroMipsR6` cannot find correct op-codes and as a result the
backend uses mips32 variant of the instructions encoding.

The patch fixes this problem by adding the StdMMR6Rel tag and check
instructions encoding in the test case.

Differential revision: https://reviews.llvm.org/D51482
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@346737 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Mips/MicroMips32r6InstrInfo.td
lib/Target/Mips/MipsInstrFPU.td
test/CodeGen/Mips/micromips-mtc-mfc.ll [new file with mode: 0644]