]> granicus.if.org Git - llvm/commit
[DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector...
authorCraig Topper <craig.topper@intel.com>
Mon, 4 Mar 2019 19:12:16 +0000 (19:12 +0000)
committerCraig Topper <craig.topper@intel.com>
Mon, 4 Mar 2019 19:12:16 +0000 (19:12 +0000)
commitb6ab93e6a5dc1545b43de403194ebae0b96d87c0
tree8befd73923bff3cce6463a66f55be0001de91600
parent328c03355279f68186ee6230ba73c79b69b6d082
[DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector constants)) between legalize types and legalize dag.

This patch enables combining integer bitcasts of integer build vectors when the new scalar type is legal. I've avoided floating point because the implementation bitcasts float to int along the way and we would need to check the intermediate types for legality

Differential Revision: https://reviews.llvm.org/D58884

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355324 91177308-0d34-0410-b5e6-96231b3b80d8
15 files changed:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
test/CodeGen/AArch64/fold-constants.ll
test/CodeGen/SystemZ/vec-extract-01.ll
test/CodeGen/X86/memcmp-optsize.ll
test/CodeGen/X86/memcmp.ll
test/CodeGen/X86/vec_insert-7.ll
test/CodeGen/X86/vec_zero_cse.ll
test/CodeGen/X86/vector-shift-ashr-sub128.ll
test/CodeGen/X86/vector-shift-lshr-sub128.ll
test/CodeGen/X86/vector-shift-shl-sub128.ll
test/CodeGen/X86/vselect-avx.ll
test/CodeGen/X86/widen_arith-4.ll
test/CodeGen/X86/widen_arith-5.ll
test/CodeGen/X86/widen_cast-1.ll
test/CodeGen/X86/widen_shuffle-1.ll