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author	Matt Arsenault <Matthew.Arsenault@amd.com>
	Mon, 1 Jul 2019 13:22:04 +0000 (13:22 +0000)
committer	Matt Arsenault <Matthew.Arsenault@amd.com>
	Mon, 1 Jul 2019 13:22:04 +0000 (13:22 +0000)
commit	b68b21c025ac6d4fa1dd64016162d5e7ae0b8b82
tree	50425b1155fdf9487282bb6181403180a5f9f861	tree \| snapshot
parent	6b9ac8abd2da333e325f959f9427e6bc1d717610	commit \| diff

GlobalISel: Add GINodeEquiv for min/max

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364759 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Target/GlobalISel/SelectionDAGCompat.td		diff \| blob \| history
test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir	[new file with mode: 0644]	blob
test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir	[new file with mode: 0644]	blob
test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir	[new file with mode: 0644]	blob
test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir	[new file with mode: 0644]	blob

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