granicus.if.org Git - llvm/commit

]> granicus.if.org Git - llvm/commit

author	Daniel Sanders <daniel.sanders@imgtec.com>
	Tue, 15 Sep 2015 10:02:16 +0000 (10:02 +0000)
committer	Daniel Sanders <daniel.sanders@imgtec.com>
	Tue, 15 Sep 2015 10:02:16 +0000 (10:02 +0000)
commit	b57c2dc74617ba8255bed770f44d53415c3bf32c
tree	f5a8757bdd769860a8677baf0ba84e3ae457ee7a	tree \| snapshot
parent	5d1cac1aa28e02fda6be52b5ddf4940085df64d9	commit \| diff

[mips] Added support for various EVA ASE instructions.

Summary:
Added support for the following instructions:

CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF

This required adding some infrastructure for the EVA ASE.

Patch by Scott Egerton.

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11139

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247669 91177308-0d34-0410-b5e6-96231b3b80d8

29 files changed:

lib/Target/Mips/Disassembler/MipsDisassembler.cpp		diff \| blob \| history
lib/Target/Mips/Mips.td		diff \| blob \| history
lib/Target/Mips/Mips32r6InstrInfo.td		diff \| blob \| history
lib/Target/Mips/MipsEVAInstrFormats.td	[new file with mode: 0644]	blob
lib/Target/Mips/MipsEVAInstrInfo.td	[new file with mode: 0644]	blob
lib/Target/Mips/MipsInstrInfo.td		diff \| blob \| history
lib/Target/Mips/MipsSchedule.td		diff \| blob \| history
lib/Target/Mips/MipsSubtarget.cpp		diff \| blob \| history
lib/Target/Mips/MipsSubtarget.h		diff \| blob \| history
test/MC/Disassembler/Mips/eva/valid_R6-eva.txt	[new file with mode: 0644]	blob
test/MC/Disassembler/Mips/eva/valid_preR6-eva.txt	[new file with mode: 0644]	blob
test/MC/Mips/eva/invalid-noeva-wrong-error.s	[new file with mode: 0644]	blob
test/MC/Mips/eva/invalid-noeva.s	[new file with mode: 0644]	blob
test/MC/Mips/eva/invalid_R6.s	[new file with mode: 0644]	blob
test/MC/Mips/eva/valid_R6.s	[new file with mode: 0644]	blob
test/MC/Mips/eva/valid_preR6.s	[new file with mode: 0644]	blob
test/MC/Mips/mips32/valid.s		diff \| blob \| history
test/MC/Mips/mips32r2/valid.s		diff \| blob \| history
test/MC/Mips/mips32r3/valid.s		diff \| blob \| history
test/MC/Mips/mips32r5/valid.s		diff \| blob \| history
test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s		diff \| blob \| history
test/MC/Mips/mips32r6/valid.s		diff \| blob \| history
test/MC/Mips/mips64/valid.s		diff \| blob \| history
test/MC/Mips/mips64r2/valid.s		diff \| blob \| history
test/MC/Mips/mips64r3/valid.s		diff \| blob \| history
test/MC/Mips/mips64r5/valid.s		diff \| blob \| history
test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s		diff \| blob \| history
test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s		diff \| blob \| history
test/MC/Mips/mips64r6/valid.s		diff \| blob \| history

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