]> granicus.if.org Git - llvm/commit
AMDGPU: Add 24-bit mul intrinsics
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 15 Jul 2019 17:50:31 +0000 (17:50 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 15 Jul 2019 17:50:31 +0000 (17:50 +0000)
commitb508009134c1349367df52d96bf8d8db6e7f7247
tree6e3d881c5486f3bf57a2a8e05a941a859dbb671c
parent260d1e96f9cc90a6b2cef28c317f0213cdd898c0
AMDGPU: Add 24-bit mul intrinsics

Insert these during codegenprepare.

This works around a DAG issue where generic combines eliminate the and
asserting the high bits are zero, which then exposes an unknown read
source to the mul combine. It doesn't worth the hassle of trying to
insert an AssertZext or something to try to deal with it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366094 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/IR/IntrinsicsAMDGPU.td
lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
lib/Target/AMDGPU/SIISelLowering.cpp
test/CodeGen/AMDGPU/amdgpu-codegenprepare-mul24.ll [new file with mode: 0644]
test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll [new file with mode: 0644]
test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll [new file with mode: 0644]
test/CodeGen/AMDGPU/mad_uint24.ll
test/CodeGen/AMDGPU/mul.i16.ll
test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll