]> granicus.if.org Git - llvm/commit
[AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate...
authorAmara Emerson <aemerson@apple.com>
Wed, 3 Jul 2019 01:49:06 +0000 (01:49 +0000)
committerAmara Emerson <aemerson@apple.com>
Wed, 3 Jul 2019 01:49:06 +0000 (01:49 +0000)
commitb4dc9c31c2ac81a51da71247b6a10e7796ed696f
treee90d4fcc41e36fbced0e96420f25f0f53eb8e685
parentadf8ddb23a221424eac1c3f208ba4107380fcb47
[AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate forms.

There are two main issues preventing us from generating immediate form shifts:
1) We have partial SelectionDAG imported support for G_ASHR and G_LSHR shift
immediate forms, but they currently don't work because the amount type is
expected to be an s64 constant, but we only legalize them to have homogenous
types.

To deal with this, first we introduce a custom legalizer to *only* custom legalize
s32 shifts which have a constant operand into a s64.

There is also an additional artifact combiner to fold zexts(g_constant) to a
larger G_CONSTANT if it's legal, a counterpart to the anyext version committed
in an earlier patch.

2) For G_SHL the importer can't cope with the pattern. For this I introduced an
early selection phase in the arm64 selector to select these forms manually
before the tablegen selector pessimizes it to a register-register variant.

Differential Revision: https://reviews.llvm.org/D63910

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364994 91177308-0d34-0410-b5e6-96231b3b80d8
17 files changed:
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
lib/Target/AArch64/AArch64GenRegisterBankInfo.def
lib/Target/AArch64/AArch64InstructionSelector.cpp
lib/Target/AArch64/AArch64LegalizerInfo.cpp
lib/Target/AArch64/AArch64LegalizerInfo.h
lib/Target/AArch64/AArch64RegisterBankInfo.cpp
lib/Target/AArch64/AArch64RegisterBankInfo.h
test/CodeGen/AArch64/GlobalISel/legalize-div.mir
test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir [new file with mode: 0644]
test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir [new file with mode: 0644]
test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir