]> granicus.if.org Git - llvm/commit
GlobalISel: Add target pre-isel instructions
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 7 Oct 2019 18:43:29 +0000 (18:43 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 7 Oct 2019 18:43:29 +0000 (18:43 +0000)
commitb4bef9ad2f10db0cda5110902dc8f10d6bc2089a
treeea0bc6fdfd48369ec089518458de524613fb2423
parent81e339197ecc045d5b73c2365740f775aa81fd92
GlobalISel: Add target pre-isel instructions

Allows targets to introduce regbankselectable
pseudo-instructions. Currently the closet feature to this is an
intrinsic. However this requires creating a public intrinsic
declaration. This litters the public intrinsic namespace with
operations we don't necessarily want to expose to IR producers, and
would rather leave as private to the backend.

Use a new instruction bit. A previous attempt tried to keep using enum
value ranges, but it turned into a mess.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373937 91177308-0d34-0410-b5e6-96231b3b80d8
15 files changed:
include/llvm/CodeGen/MachineInstr.h
include/llvm/MC/MCInstrDesc.h
include/llvm/Target/GenericOpcodes.td
include/llvm/Target/Target.td
lib/CodeGen/GlobalISel/RegBankSelect.cpp
lib/Target/AMDGPU/AMDGPUGISel.td
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
lib/Target/AMDGPU/SIInstrInfo.cpp
lib/Target/AMDGPU/SIInstructions.td
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir [new file with mode: 0644]
test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir [new file with mode: 0644]
utils/TableGen/CodeGenInstruction.cpp
utils/TableGen/CodeGenInstruction.h
utils/TableGen/InstrInfoEmitter.cpp