]> granicus.if.org Git - llvm/commit
[X86] Add the vector integer min/max instructions to isAssociativeAndCommutative.
authorCraig Topper <craig.topper@intel.com>
Wed, 5 Jun 2019 18:25:09 +0000 (18:25 +0000)
committerCraig Topper <craig.topper@intel.com>
Wed, 5 Jun 2019 18:25:09 +0000 (18:25 +0000)
commitb342c7ebe86cb513ecde35e5034ac3071a540183
treeb0ba49a15b51cd139137a8b27b6f080b43b9b245
parent999ea6229b3ae8dd3edec0fc167aa7f124b54bcf
[X86] Add the vector integer min/max instructions to isAssociativeAndCommutative.

As far as I know these should be freely reassociatable just like
the floating point MAXC/MINC instructions.

The *reduce* test changes are largely regressions and caused by
the "generic" CPU we default to not having a scheduler model.

The machine-combiner-int-vec.ll test shows the positive benefits
of this change.

Differential Revision: https://reviews.llvm.org/D62787

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362629 91177308-0d34-0410-b5e6-96231b3b80d8
14 files changed:
lib/Target/X86/X86InstrInfo.cpp
test/CodeGen/X86/horizontal-reduce-smax.ll
test/CodeGen/X86/horizontal-reduce-smin.ll
test/CodeGen/X86/horizontal-reduce-umax.ll
test/CodeGen/X86/horizontal-reduce-umin.ll
test/CodeGen/X86/machine-combiner-int-vec.ll
test/CodeGen/X86/vector-reduce-smax-widen.ll
test/CodeGen/X86/vector-reduce-smax.ll
test/CodeGen/X86/vector-reduce-smin-widen.ll
test/CodeGen/X86/vector-reduce-smin.ll
test/CodeGen/X86/vector-reduce-umax-widen.ll
test/CodeGen/X86/vector-reduce-umax.ll
test/CodeGen/X86/vector-reduce-umin-widen.ll
test/CodeGen/X86/vector-reduce-umin.ll