]> granicus.if.org Git - llvm/commit
[mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC
authorSimon Atanasyan <simon@atanasyan.com>
Tue, 9 Jul 2019 15:48:05 +0000 (15:48 +0000)
committerSimon Atanasyan <simon@atanasyan.com>
Tue, 9 Jul 2019 15:48:05 +0000 (15:48 +0000)
commitb312777f63ad526b0e9955ea21eeffa6736706e8
tree5af5b81890ff2494bad02dc382e870eaea624fdd
parent73a92e6348546bc12fd42091a0e85d18ddd40968
[mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC

Support for 64-bit coprocessors on a 32-bit architecture
was added in `MIPS32 R2`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365507 91177308-0d34-0410-b5e6-96231b3b80d8
80 files changed:
test/CodeGen/Mips/abiflags32.ll
test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll
test/CodeGen/Mips/cconv/return-hard-float.ll
test/CodeGen/Mips/cfi_offset.ll
test/CodeGen/Mips/fp-contract.ll
test/CodeGen/Mips/fp64a.ll
test/CodeGen/Mips/msa/2r.ll
test/CodeGen/Mips/msa/2r_vector_scalar.ll
test/CodeGen/Mips/msa/2rf.ll
test/CodeGen/Mips/msa/2rf_exup.ll
test/CodeGen/Mips/msa/2rf_float_int.ll
test/CodeGen/Mips/msa/2rf_fq.ll
test/CodeGen/Mips/msa/2rf_int_float.ll
test/CodeGen/Mips/msa/2rf_tq.ll
test/CodeGen/Mips/msa/3r-a.ll
test/CodeGen/Mips/msa/3r-b.ll
test/CodeGen/Mips/msa/3r-c.ll
test/CodeGen/Mips/msa/3r-d.ll
test/CodeGen/Mips/msa/3r-i.ll
test/CodeGen/Mips/msa/3r-m.ll
test/CodeGen/Mips/msa/3r-p.ll
test/CodeGen/Mips/msa/3r-s.ll
test/CodeGen/Mips/msa/3r-v.ll
test/CodeGen/Mips/msa/3r_4r.ll
test/CodeGen/Mips/msa/3r_4r_widen.ll
test/CodeGen/Mips/msa/3rf.ll
test/CodeGen/Mips/msa/3rf_4rf.ll
test/CodeGen/Mips/msa/3rf_4rf_q.ll
test/CodeGen/Mips/msa/3rf_exdo.ll
test/CodeGen/Mips/msa/3rf_float_int.ll
test/CodeGen/Mips/msa/3rf_int_float.ll
test/CodeGen/Mips/msa/3rf_q.ll
test/CodeGen/Mips/msa/arithmetic.ll
test/CodeGen/Mips/msa/arithmetic_float.ll
test/CodeGen/Mips/msa/basic_operations_float.ll
test/CodeGen/Mips/msa/bit.ll
test/CodeGen/Mips/msa/bitcast.ll
test/CodeGen/Mips/msa/bitwise.ll
test/CodeGen/Mips/msa/bmzi_bmnzi.ll
test/CodeGen/Mips/msa/compare.ll
test/CodeGen/Mips/msa/compare_float.ll
test/CodeGen/Mips/msa/elm_copy.ll
test/CodeGen/Mips/msa/elm_cxcmsa.ll
test/CodeGen/Mips/msa/elm_insv.ll
test/CodeGen/Mips/msa/elm_move.ll
test/CodeGen/Mips/msa/elm_shift_slide.ll
test/CodeGen/Mips/msa/endian.ll
test/CodeGen/Mips/msa/frameindex.ll
test/CodeGen/Mips/msa/i10.ll
test/CodeGen/Mips/msa/i5-a.ll
test/CodeGen/Mips/msa/i5-b.ll
test/CodeGen/Mips/msa/i5-c.ll
test/CodeGen/Mips/msa/i5-m.ll
test/CodeGen/Mips/msa/i5-s.ll
test/CodeGen/Mips/msa/i5_ld_st.ll
test/CodeGen/Mips/msa/i8.ll
test/CodeGen/Mips/msa/immediates-bad.ll
test/CodeGen/Mips/msa/immediates.ll
test/CodeGen/Mips/msa/inline-asm.ll
test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll
test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll
test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll
test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
test/CodeGen/Mips/msa/shift-dagcombine.ll
test/CodeGen/Mips/msa/shift_constant_pool.ll
test/CodeGen/Mips/msa/shift_no_and.ll
test/CodeGen/Mips/msa/shuffle.ll
test/CodeGen/Mips/msa/special.ll
test/CodeGen/Mips/msa/spill.ll
test/CodeGen/Mips/msa/vec.ll
test/CodeGen/Mips/msa/vecs10.ll
test/CodeGen/Mips/stack-alignment.ll