[X86] Match the IR pattern form movmsk on SSE1 only targets where v4i32 isn't legal

[X86] Match the IR pattern form movmsk on SSE1 only targets where v4i32 isn't legal

Summary:
This patch adds a special DAG combine for SSE1 to recognize the IR pattern InstCombine gives us for movmsk. This only does the recognition for a few cases where its obvious the input won't be scalarized resulting in building a vector just do to the movmsk. I've made it separate from our existing matching for movmsk since that's called in multiple places and I didn't spend time to see if the other callers would make sense here. Plus the restrictions and additional checks would complicate that.

This fixes the case from PR42870. Buts its probably still broken the presence of logic ops feeding the movmsk pattern which would further hide the v4f32 type.

Reviewers: spatel, RKSimon, xbolva00

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65689

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368506 91177308-0d34-0410-b5e6-96231b3b80d8