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UpdateTestChecks: arm64-eabi handlind
authorRoman Lebedev <lebedev.ri@gmail.com>
Sat, 18 May 2019 12:59:56 +0000 (12:59 +0000)
committerRoman Lebedev <lebedev.ri@gmail.com>
Sat, 18 May 2019 12:59:56 +0000 (12:59 +0000)
commitae4d462582fa4a23b8ac040e2c0f9ed30e7be784
tree282c0a76ea62b55e00142170acf5d945927d4ba3tree | snapshot
parenta77280973d22b32ebd0e244ad4649946f71fa778commit | diff
UpdateTestChecks: arm64-eabi handlind

Summary:
Was looking into supporting `(srl (shl x, c1), c2)` with c1 != c2 in dagcombiner,
this test changes, but makes `update_llc_test_checks.py` unhappy

Reviewers: RKSimon

Reviewed By: RKSimon

Subscribers: javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62097

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361100 91177308-0d34-0410-b5e6-96231b3b80d8
test/CodeGen/AArch64/arm64-bitfield-extract.ll diff | blob | history
utils/UpdateTestChecks/asm.py diff | blob | history
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