]> granicus.if.org Git - llvm/commit
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
authorHans Wennborg <hans@hanshq.net>
Mon, 12 Aug 2019 14:23:13 +0000 (14:23 +0000)
committerHans Wennborg <hans@hanshq.net>
Mon, 12 Aug 2019 14:23:13 +0000 (14:23 +0000)
commitad324a1d846c77d020e25607f50152122a650672
treed1eded85e9899c4715260cb41ac031ac7dfdfe69
parenta44a1a275d42a4b2959e215c01bdc21b0434a8b5
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"

It caused assertions to fire when building Chromium:

  lib/CodeGen/LiveDebugValues.cpp:331: bool
  {anonymous}::LiveDebugValues::OpenRangesSet::empty() const: Assertion
  `Vars.empty() == VarLocs.empty() && "open ranges are inconsistent"' failed.

See https://crbug.com/992871#c3 for how to reproduce.

> Patch https://reviews.llvm.org/D43256 introduced more aggressive loop layout optimization which depends on profile information. If profile information is not available, the statically estimated profile information(generated by BranchProbabilityInfo.cpp) is used. If user program doesn't behave as BranchProbabilityInfo.cpp expected, the layout may be worse.
>
> To be conservative this patch restores the original layout algorithm in plain mode. But user can still try the aggressive layout optimization with -force-precise-rotation-cost=true.
>
> Differential Revision: https://reviews.llvm.org/D65673

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368579 91177308-0d34-0410-b5e6-96231b3b80d8
59 files changed:
lib/CodeGen/MachineBlockPlacement.cpp
test/CodeGen/AArch64/cmpxchg-idioms.ll
test/CodeGen/AArch64/tailmerging_in_mbp.ll
test/CodeGen/AMDGPU/collapse-endcf.ll
test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
test/CodeGen/AMDGPU/global_smrd_cfg.ll
test/CodeGen/AMDGPU/i1-copy-from-loop.ll
test/CodeGen/AMDGPU/indirect-addressing-si.ll
test/CodeGen/AMDGPU/loop_exit_with_xor.ll
test/CodeGen/AMDGPU/multilevel-break.ll
test/CodeGen/AMDGPU/optimize-negated-cond.ll
test/CodeGen/AMDGPU/si-annotate-cf.ll
test/CodeGen/AMDGPU/wave32.ll
test/CodeGen/AMDGPU/wqm.ll
test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
test/CodeGen/ARM/arm-and-tst-peephole.ll
test/CodeGen/ARM/atomic-cmp.ll
test/CodeGen/ARM/atomic-cmpxchg.ll
test/CodeGen/ARM/code-placement.ll
test/CodeGen/ARM/pr32578.ll
test/CodeGen/Hexagon/bug6757-endloop.ll
test/CodeGen/Hexagon/early-if-merge-loop.ll
test/CodeGen/Hexagon/prof-early-if.ll
test/CodeGen/Hexagon/redundant-branching2.ll
test/CodeGen/PowerPC/atomics-regression.ll
test/CodeGen/PowerPC/block-placement-1.mir
test/CodeGen/PowerPC/cmp_elimination.ll
test/CodeGen/PowerPC/licm-remat.ll
test/CodeGen/PowerPC/machine-pre.ll
test/CodeGen/RISCV/atomic-rmw.ll
test/CodeGen/RISCV/remat.ll
test/CodeGen/Thumb/consthoist-physical-addr.ll
test/CodeGen/Thumb/pr42760.ll
test/CodeGen/X86/block-placement.ll
test/CodeGen/X86/code_placement.ll
test/CodeGen/X86/code_placement_ignore_succ_in_inner_loop.ll
test/CodeGen/X86/code_placement_loop_rotation2.ll
test/CodeGen/X86/code_placement_no_header_change.ll
test/CodeGen/X86/conditional-tailcall.ll
test/CodeGen/X86/loop-blocks.ll
test/CodeGen/X86/loop-rotate.ll [new file with mode: 0644]
test/CodeGen/X86/lsr-loop-exit-cond.ll
test/CodeGen/X86/move_latch_to_loop_top.ll
test/CodeGen/X86/pr38185.ll
test/CodeGen/X86/ragreedy-hoist-spill.ll
test/CodeGen/X86/reverse_branches.ll
test/CodeGen/X86/speculative-load-hardening.ll
test/CodeGen/X86/tail-dup-merge-loop-headers.ll
test/CodeGen/X86/tail-dup-repeat.ll
test/CodeGen/X86/vector-shift-by-select-loop.ll
test/CodeGen/X86/widen_arith-1.ll
test/CodeGen/X86/widen_arith-2.ll
test/CodeGen/X86/widen_arith-3.ll
test/CodeGen/X86/widen_arith-4.ll
test/CodeGen/X86/widen_arith-5.ll
test/CodeGen/X86/widen_arith-6.ll
test/CodeGen/X86/widen_cast-4.ll
test/DebugInfo/X86/PR37234.ll
test/DebugInfo/X86/dbg-value-transfer-order.ll