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(parent: 490bc39) | patch
[X86] Make FeatureAVX512 imply FeatureF16C.
authorCraig Topper <craig.topper@intel.com>
Mon, 6 Nov 2017 22:49:04 +0000 (22:49 +0000)
committerCraig Topper <craig.topper@intel.com>
Mon, 6 Nov 2017 22:49:04 +0000 (22:49 +0000)
commitacf8758c20c2fd51db8dfb533dfc01941f8112e1
tree7784bcf39832c0168e3a705995cab344be12d110tree | snapshot
parent490bc3940dd4098ef1cd81c1f3f19203b4317d3fcommit | diff
[X86] Make FeatureAVX512 imply FeatureF16C.

The EVEX to VEX pass is already assuming this is true under AVX512VL. We had special patterns to use zmm instructions if VLX and F16C weren't available.

Instead just make AVX512 imply F16C to make the EVEX to VEX behavior explicitly legal and remove the extra patterns.

All known CPUs with AVX512 have F16C so this should safe for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317521 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86.td diff | blob | history
lib/Target/X86/X86ISelLowering.cpp diff | blob | history
lib/Target/X86/X86InstrAVX512.td diff | blob | history
lib/Target/X86/X86InstrInfo.td diff | blob | history
test/CodeGen/X86/vec_fp_to_int.ll diff | blob | history
test/CodeGen/X86/vector-half-conversions.ll diff | blob | history
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