Change some optimization settings so that imm8 optimizations actually get

Change some optimization settings so that imm8 optimizations actually get
triggered for more cases and optimize from 64-bit down to 32-bit for 64-bit
mov instructions.  This change means that mov reg64, constant will be
auto-sized up to 64 bits, but mov reg64, expr/symbol will default to 32 bits.
You must use mov reg64, qword expr/symbol if you need 64 bits, or in GAS
mode use movabsq expr/symbol, reg64.

This makes the generated code smaller and default most usages into 32-bit
relocations appropriate for ELF64 and Win64.  Right now, 32-bit unsigned
relocs are generated instead of 32-bit signed; this will need to be fixed.

* x86arch.h (x86_insn.postop): Add X86_POSTOP_SIGNEXT_IMM32.
* x86bc.c (x86_bc_insn_resolve): Implement.
* x86id.re (OPAP_SImm32Avail): New flag.
(MOD_Op2AddSp): New modifier to encode spare directly into 2nd opcode byte.
(arith_insn): Use MOD_Op2AddSp and add forced-size override forms.
(mov_insn): Use OPAP_SImm32Avail and add forced-size override form.
(yasm_x86__finalize_insn): Implement new flag and modifier.

Fix up testcases for changes.

svn path=/trunk/yasm/; revision=1314