]> granicus.if.org Git - llvm/commit
AMDGPU/GlobalISel: Allow scalar s1 and/or/xor
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 15 Jul 2019 20:20:18 +0000 (20:20 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 15 Jul 2019 20:20:18 +0000 (20:20 +0000)
commita985f4ba1574974d3fa9b7d7bfd6675a776f133a
treeecc3001c224a73661b2088abb687c01fb4fd5a4e
parent8060f843435145ff151ecc9e5f1521c7966cffaf
AMDGPU/GlobalISel: Allow scalar s1 and/or/xor

If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to
whether the result is 0. If the inputs are SCC, these can be copied to
a 32-bit SGPR to produce an SCC result.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366125 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir [new file with mode: 0644]
test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir [new file with mode: 0644]
test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir