[globalisel][tablegen] Skip src child predicates

[globalisel][tablegen] Skip src child predicates

The GlobalISel TableGen backend didn't check for predicates on the
source children. This caused it to generate code for ARM patterns such
as SMLABB or similar, but without properly checking for the sext_16_node
part of the operands. This in turn meant that we would select SMLABB
instead of MLA for simple sequences such as s32 + s32 * s32, which is
wrong (we want a MLA on the full operands, not just their bottom 16
bits).

This patch forces TableGen to skip patterns with predicates on the src
children, so it doesn't generate code for SMLABB and other similar ARM
instructions at all anymore. AArch64 and X86 are not affected.

Differential Revision: https://reviews.llvm.org/D39554

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317313 91177308-0d34-0410-b5e6-96231b3b80d8