[SelectionDAG] Add asserts to verify the vectorness of input and output types of...

[SelectionDAG] Add asserts to verify the vectorness of input and output types of TRUNCATE/ZERO_EXTEND/ANY_EXTEND/SIGN_EXTEND agree

As a result of the underlying cause of PR41678 we created an ANY_EXTEND node with a scalar result type and v1i1 input type. Ideally we would have asserted for this instead of letting it go through to instruction selection and generate bad machine IR

Differential Revision: https://reviews.llvm.org/D61463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359836 91177308-0d34-0410-b5e6-96231b3b80d8