[ARM] Correct register for narrowing and widening MVE loads and stores.

[ARM] Correct register for narrowing and widening MVE loads and stores.

The widening and narrowing MVE instructions like VLDRH.32 are only permitted to
use low tGPR registers. This means that if they are used for a stack slot,
where the register used is only decided during frame setup, we need to be able
to correctly pick a thumb1 register over a normal GPR.

This attempts to add the required logic into eliminateFrameIndex and
rewriteT2FrameIndex, only picking the FrameReg if it is a valid register for
the operands register class, and picking a valid scratch register for the
register class.

Differential Revision: https://reviews.llvm.org/D66285

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369108 91177308-0d34-0410-b5e6-96231b3b80d8