]> granicus.if.org Git - llvm/commit
[X86] Connect the default fpsr and dirflag clobbers in inline assembly to the registe...
authorCraig Topper <craig.topper@intel.com>
Tue, 5 Feb 2019 06:13:06 +0000 (06:13 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 5 Feb 2019 06:13:06 +0000 (06:13 +0000)
commita0e049148f8cb1501e6ec071027f5243a76be91b
treea6b04a4383079ad5f205edba6e59300b30918e39
parenta0df8c82235a05b60414705487b43b877e86d9e1
[X86] Connect the default fpsr and dirflag clobbers in inline assembly to the registers we have defined for them.

Summary:
We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly.

This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that.

Reviewers: rnk

Reviewed By: rnk

Subscribers: eraman, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D57641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353141 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86RegisterInfo.td
test/CodeGen/X86/inline-asm-default-clobbers.ll [new file with mode: 0644]