]> granicus.if.org Git - llvm/commit
AMDGPU: Allow SIShrinkInstructions to work in non-SSA
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 10 Jul 2017 19:53:57 +0000 (19:53 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 10 Jul 2017 19:53:57 +0000 (19:53 +0000)
commita038a8340c1fd7497d166cb82d46945bef672f1d
tree516b383d1722048b87e31c46db1fd89fc45f97eb
parent723196608916531f9a61e834f649f083964bb83f
AMDGPU: Allow SIShrinkInstructions to work in non-SSA

Immediates can be folded as long as the immediate is a vreg.

Also undo commuting instructions if it didn't fold an immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307575 91177308-0d34-0410-b5e6-96231b3b80d8
69 files changed:
lib/Target/AMDGPU/SIShrinkInstructions.cpp
test/CodeGen/AMDGPU/add.i16.ll
test/CodeGen/AMDGPU/add.v2i16.ll
test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
test/CodeGen/AMDGPU/ctlz.ll
test/CodeGen/AMDGPU/ds_read2.ll
test/CodeGen/AMDGPU/ds_read2_superreg.ll
test/CodeGen/AMDGPU/ds_read2st64.ll
test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll
test/CodeGen/AMDGPU/fabs.f16.ll
test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
test/CodeGen/AMDGPU/fadd.f16.ll
test/CodeGen/AMDGPU/fdiv.f16.ll
test/CodeGen/AMDGPU/fdiv.ll
test/CodeGen/AMDGPU/fma-combine.ll
test/CodeGen/AMDGPU/fmax_legacy.ll
test/CodeGen/AMDGPU/fmed3.ll
test/CodeGen/AMDGPU/fmin_legacy.ll
test/CodeGen/AMDGPU/fmul.f16.ll
test/CodeGen/AMDGPU/fmuladd.f16.ll
test/CodeGen/AMDGPU/fmuladd.f32.ll
test/CodeGen/AMDGPU/fneg-combines.ll
test/CodeGen/AMDGPU/fneg-fabs.f16.ll
test/CodeGen/AMDGPU/fneg.f16.ll
test/CodeGen/AMDGPU/fpext.f16.ll
test/CodeGen/AMDGPU/fptosi.f16.ll
test/CodeGen/AMDGPU/fptoui.f16.ll
test/CodeGen/AMDGPU/fptrunc.f16.ll
test/CodeGen/AMDGPU/fract.ll
test/CodeGen/AMDGPU/frem.ll
test/CodeGen/AMDGPU/fsub.f16.ll
test/CodeGen/AMDGPU/fsub.ll
test/CodeGen/AMDGPU/half.ll
test/CodeGen/AMDGPU/immv216.ll
test/CodeGen/AMDGPU/llvm.ceil.f16.ll
test/CodeGen/AMDGPU/llvm.cos.f16.ll
test/CodeGen/AMDGPU/llvm.exp2.f16.ll
test/CodeGen/AMDGPU/llvm.floor.f16.ll
test/CodeGen/AMDGPU/llvm.fma.f16.ll
test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
test/CodeGen/AMDGPU/llvm.log2.f16.ll
test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
test/CodeGen/AMDGPU/llvm.minnum.f16.ll
test/CodeGen/AMDGPU/llvm.rint.f16.ll
test/CodeGen/AMDGPU/llvm.round.ll
test/CodeGen/AMDGPU/llvm.sin.f16.ll
test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
test/CodeGen/AMDGPU/llvm.trunc.f16.ll
test/CodeGen/AMDGPU/mad-combine.ll
test/CodeGen/AMDGPU/madak.ll
test/CodeGen/AMDGPU/madmk.ll
test/CodeGen/AMDGPU/rsq.ll
test/CodeGen/AMDGPU/scalar_to_vector.ll
test/CodeGen/AMDGPU/scratch-simple.ll
test/CodeGen/AMDGPU/sdwa-peephole.ll
test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
test/CodeGen/AMDGPU/setcc-fneg-constant.ll
test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
test/CodeGen/AMDGPU/sminmax.ll
test/CodeGen/AMDGPU/sub.i16.ll
test/CodeGen/AMDGPU/sub.v2i16.ll
test/CodeGen/AMDGPU/usubo.ll
test/CodeGen/AMDGPU/v_mac.ll
test/CodeGen/AMDGPU/v_mac_f16.ll
test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir [new file with mode: 0644]
test/CodeGen/AMDGPU/xor.ll
test/CodeGen/AMDGPU/zext-i64-bit-operand.ll
test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir