]> granicus.if.org Git - llvm/commit
[X86][SKL] Updated scheduling information for the SkylakeClient target
authorGadi Haber <gadi.haber@intel.com>
Tue, 17 Oct 2017 06:47:04 +0000 (06:47 +0000)
committerGadi Haber <gadi.haber@intel.com>
Tue, 17 Oct 2017 06:47:04 +0000 (06:47 +0000)
commit9e68191ef66c8a6bfacb80ab9d762bac0152d130
tree7c31d098c69607a2f9991455d2a7705ae3c1d498
parentc596921f1a1a2aad1c325c27582977500b4762a0
[X86][SKL] Updated scheduling information for the SkylakeClient target

Updated the scheduling information for the SkylakeClient target with the following changes:

1. regrouped the instructions after adding load and store latencies.
2. regrouped the instructions after adding identified missing ports in several groups.
The changes were made after revisiting the latencies impact of all the load and store uOps.

Reviewers: zvi, RKSimon, craig.topper
Differential Revision: https://reviews.llvm.org/D38727

Change-Id: I778a308cc11e490e8fa5e27e2047412a1dca029f

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315978 91177308-0d34-0410-b5e6-96231b3b80d8
19 files changed:
lib/Target/X86/X86SchedSkylakeClient.td
test/CodeGen/X86/aes-schedule.ll
test/CodeGen/X86/avx-schedule.ll
test/CodeGen/X86/avx2-schedule.ll
test/CodeGen/X86/bmi-schedule.ll
test/CodeGen/X86/bmi2-schedule.ll
test/CodeGen/X86/f16c-schedule.ll
test/CodeGen/X86/fma-schedule.ll
test/CodeGen/X86/lea32-schedule.ll
test/CodeGen/X86/lea64-schedule.ll
test/CodeGen/X86/lzcnt-schedule.ll
test/CodeGen/X86/movbe-schedule.ll
test/CodeGen/X86/popcnt-schedule.ll
test/CodeGen/X86/sse-schedule.ll
test/CodeGen/X86/sse2-schedule.ll
test/CodeGen/X86/sse3-schedule.ll
test/CodeGen/X86/sse41-schedule.ll
test/CodeGen/X86/sse42-schedule.ll
test/CodeGen/X86/ssse3-schedule.ll