granicus.if.org Git - llvm/commit

]> granicus.if.org Git - llvm/commit

author	Yi-Hong Lyu <Yi-Hong.Lyu@ibm.com>
	Tue, 23 Jul 2019 19:11:07 +0000 (19:11 +0000)
committer	Yi-Hong Lyu <Yi-Hong.Lyu@ibm.com>
	Tue, 23 Jul 2019 19:11:07 +0000 (19:11 +0000)
commit	999fc95b91f9b53ab7a5d922fca2488560982db9
tree	645eb018ea38fcdc3f2b965edf318de827579a91	tree \| snapshot
parent	e614cf3e31f9e4c488a5dfc4c755f60c87007c3e	commit \| diff

[PowerPC] Remove redundant load immediate instructions

Currently PowerPC backend emits code like this:

  r3 = li 0
  std r3, 264(r1)
  r3 = li 0
  std r3, 272(r1)

This patch fixes that and other cases where a register already contains a value that is loaded so we will get:

  r3 = li 0
  std r3, 264(r1)
  std r3, 272(r1)

Differential Revision: https://reviews.llvm.org/D64220

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366840 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCPreEmitPeephole.cpp		diff \| blob \| history
test/CodeGen/PowerPC/remove-redundant-load-imm.ll	[new file with mode: 0644]	blob
test/CodeGen/PowerPC/remove-redundant-load-imm.mir	[new file with mode: 0644]	blob

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