]> granicus.if.org Git - llvm/commit
[X86] Call lowerShuffleAsBitMask for 512-bit vectors in lowerShuffleAsBlend.
authorCraig Topper <craig.topper@intel.com>
Wed, 20 Mar 2019 21:30:20 +0000 (21:30 +0000)
committerCraig Topper <craig.topper@intel.com>
Wed, 20 Mar 2019 21:30:20 +0000 (21:30 +0000)
commit98e0aa0b32cd4bc2dcd6f5e2536e11ddd979156c
tree7086d9f56f1b0093ffae17b92f9a729963b9c1cc
parent2213c42310b0c3c46ef028560e9772c0f6a5dcff
[X86] Call lowerShuffleAsBitMask for 512-bit vectors in lowerShuffleAsBlend.

This patch enables the use of lowerShuffleAsBitMask for 512-bit blends before
falling back to move immedate, GPR to k-register, and masked op.

I had to make some changes to support v8i64 when i64 is not a legal type. And to
support floating point types.

This trades a load for the move immediate and GPR move which is higher latency.
But its probably better for register pressure not having to hop through other
register classes. The load+and should play better with LICM and
rematerialization I think.

Differential Revision: https://reviews.llvm.org/D59479

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356618 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/avx512-mask-op.ll
test/CodeGen/X86/merge-consecutive-loads-512.ll
test/CodeGen/X86/vector-shuffle-512-v32.ll