Merge branch 'bugfix/rename_clk_rst_bits_for_spi' into 'master'
authorJiang Jiang Jian <jack@espressif.com>
Tue, 15 May 2018 01:49:56 +0000 (09:49 +0800)
committerJiang Jiang Jian <jack@espressif.com>
Tue, 15 May 2018 01:49:56 +0000 (09:49 +0800)
commit97a228e6abf1d7a75f696c1e40098a5e1c670d52
treeb37bafc933a81bba6399c88faf9aed025ac3a600
parent6adaeb0048d75eecf5f43040645b4882b4e3069d
parentc384fa24924914d27f8b31ac23e35d6350b752be
Merge branch 'bugfix/rename_clk_rst_bits_for_spi' into 'master'

rename clock enable and reset bits for SPI modules

See merge request idf/esp-idf!2293