]> granicus.if.org Git - llvm/commit
[ARM] Add v8m.base pattern for add negative imm
authorSam Parker <sam.parker@arm.com>
Mon, 11 Feb 2019 11:35:42 +0000 (11:35 +0000)
committerSam Parker <sam.parker@arm.com>
Mon, 11 Feb 2019 11:35:42 +0000 (11:35 +0000)
commit946a92e5fadbef511a62c74efb84cd47cc4233b1
tree3a294e6a70fe60dc56839e4a0f11250ca926fb82
parenta0ecdf4bba1ba47b4dd8550c5a8c4a3a9183832d
[ARM] Add v8m.base pattern for add negative imm

The v8m.base ISA contains movw, which can operate on an unsigned
16-bit value. Add the pattern that converts an add with a negative
value, that could fit into 16-bits when negated, into a sub with that
positive value.

Differential Revision: https://reviews.llvm.org/D57942

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353692 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMInstrThumb2.td
test/CodeGen/ARM/sub.ll