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AMDGPU: Use tablegen pattern for sendmsg intrinsics
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 1 Aug 2019 18:27:11 +0000 (18:27 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 1 Aug 2019 18:27:11 +0000 (18:27 +0000)
commit937a1b0fd29bc5fde97510729a7b5ff378280a1a
treec5b3bae012efaa253a40d1d7fb166789438a460dtree | snapshot
parentd527e646408b6ef4933e231cf5d9242c41033876commit | diff
AMDGPU: Use tablegen pattern for sendmsg intrinsics

Since this now emits a direct copy to m0, SIFixSGPRCopies has to
handle a physical register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367593 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/IR/IntrinsicsAMDGPU.td diff | blob | history
lib/Target/AMDGPU/SIFixSGPRCopies.cpp diff | blob | history
lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
lib/Target/AMDGPU/SOPInstructions.td diff | blob | history
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