]> granicus.if.org Git - llvm/commit
projects / llvm / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 893a416) | patch
[X86] Pass the right VT to the getZeroExtendInReg introduced in r321398
authorCraig Topper <craig.topper@intel.com>
Sat, 23 Dec 2017 06:52:03 +0000 (06:52 +0000)
committerCraig Topper <craig.topper@intel.com>
Sat, 23 Dec 2017 06:52:03 +0000 (06:52 +0000)
commit9363e85e02d9e70e78fae248c1f62d44cd6fc19f
tree88b6fad6cb9819ec114ad897f7374a67354f42a1tree | snapshot
parent893a41656b527af1b00a1f9e5c8fcecfff62e4b6commit | diff
[X86] Pass the right VT to the getZeroExtendInReg introduced in r321398

Apparently we don't have tests for this which I didn't realize before. I'll try to fix that but wanted to fix the obvious bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321399 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp diff | blob | history
Unnamed repository; edit this file 'description' to name the repository.