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[ARM] Don't form "ands" when it isn't scheduled correctly.
authorEli Friedman <efriedma@quicinc.com>
Fri, 22 Mar 2019 20:49:15 +0000 (20:49 +0000)
committerEli Friedman <efriedma@quicinc.com>
Fri, 22 Mar 2019 20:49:15 +0000 (20:49 +0000)
commit925f59138d80ee5097af21e5e5d2eda1f75e0794
treeae6e431fa1ffdf4dd31eb21458d85d8887b67adftree | snapshot
parent93b589a73dacf583c9651060c519480a7a70d334commit | diff
[ARM] Don't form "ands" when it isn't scheduled correctly.

In r322972/r323136, the iteration here was changed to catch cases at the
beginning of a basic block... but we accidentally deleted an important
safety check.  Restore that check to the way it was.

Fixes https://bugs.llvm.org/show_bug.cgi?id=41116

Differential Revision: https://reviews.llvm.org/D59680

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356809 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMBaseInstrInfo.cpp diff | blob | history
test/CodeGen/ARM/tst-peephole.mir [new file with mode: 0644] blob
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