]> granicus.if.org Git - llvm/commit
[CodeGen] Rename MachineInstrBuilder::addOperand. NFC
authorDiana Picus <diana.picus@linaro.org>
Fri, 13 Jan 2017 09:58:52 +0000 (09:58 +0000)
committerDiana Picus <diana.picus@linaro.org>
Fri, 13 Jan 2017 09:58:52 +0000 (09:58 +0000)
commit8a47810cd6bf8c0803b2c0076b292f042a7b6d8f
treeb4ac3586658e5c3bf3d7fc17dc088a626b0d77c8
parent0aacbaa85171534f34d7df03b028b363ec0fa066
[CodeGen] Rename MachineInstrBuilder::addOperand. NFC

Rename from addOperand to just add, to match the other method that has been
added to MachineInstrBuilder for adding more than just 1 operand.

See https://reviews.llvm.org/D28057 for the whole discussion.

Differential Revision: https://reviews.llvm.org/D28556

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291891 91177308-0d34-0410-b5e6-96231b3b80d8
66 files changed:
include/llvm/CodeGen/MachineInstrBuilder.h
lib/CodeGen/ImplicitNullChecks.cpp
lib/CodeGen/LiveDebugVariables.cpp
lib/CodeGen/PatchableFunction.cpp
lib/CodeGen/SelectionDAG/FastISel.cpp
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
lib/CodeGen/TargetInstrInfo.cpp
lib/CodeGen/TargetLoweringBase.cpp
lib/CodeGen/TwoAddressInstructionPass.cpp
lib/CodeGen/XRayInstrumentation.cpp
lib/Target/AArch64/AArch64CallLowering.cpp
lib/Target/AArch64/AArch64ConditionOptimizer.cpp
lib/Target/AArch64/AArch64ConditionalCompares.cpp
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
lib/Target/AArch64/AArch64FrameLowering.cpp
lib/Target/AArch64/AArch64InstrInfo.cpp
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
lib/Target/AMDGPU/R600ISelLowering.cpp
lib/Target/AMDGPU/SIFixSGPRCopies.cpp
lib/Target/AMDGPU/SIISelLowering.cpp
lib/Target/AMDGPU/SIInsertSkips.cpp
lib/Target/AMDGPU/SIInstrInfo.cpp
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
lib/Target/AMDGPU/SILowerControlFlow.cpp
lib/Target/AMDGPU/SILowerI1Copies.cpp
lib/Target/AMDGPU/SIRegisterInfo.cpp
lib/Target/AMDGPU/SIShrinkInstructions.cpp
lib/Target/ARM/ARMBaseInstrInfo.cpp
lib/Target/ARM/ARMConstantIslandPass.cpp
lib/Target/ARM/ARMExpandPseudoInsts.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
lib/Target/ARM/Thumb1FrameLowering.cpp
lib/Target/ARM/Thumb2SizeReduction.cpp
lib/Target/AVR/AVRExpandPseudoInsts.cpp
lib/Target/Hexagon/HexagonBitSimplify.cpp
lib/Target/Hexagon/HexagonEarlyIfConv.cpp
lib/Target/Hexagon/HexagonExpandCondsets.cpp
lib/Target/Hexagon/HexagonFixupHwLoops.cpp
lib/Target/Hexagon/HexagonFrameLowering.cpp
lib/Target/Hexagon/HexagonGenMux.cpp
lib/Target/Hexagon/HexagonInstrInfo.cpp
lib/Target/Hexagon/HexagonOptAddrMode.cpp
lib/Target/Lanai/LanaiInstrInfo.cpp
lib/Target/MSP430/MSP430BranchSelector.cpp
lib/Target/Mips/MipsInstrInfo.cpp
lib/Target/Mips/MipsSEISelLowering.cpp
lib/Target/NVPTX/NVPTXPeephole.cpp
lib/Target/PowerPC/PPCInstrInfo.cpp
lib/Target/PowerPC/PPCMIPeephole.cpp
lib/Target/PowerPC/PPCVSXCopy.cpp
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
lib/Target/SystemZ/SystemZElimCompare.cpp
lib/Target/SystemZ/SystemZISelLowering.cpp
lib/Target/SystemZ/SystemZInstrInfo.cpp
lib/Target/SystemZ/SystemZLongBranch.cpp
lib/Target/SystemZ/SystemZShortenInst.cpp
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp
lib/Target/X86/X86CallFrameOptimization.cpp
lib/Target/X86/X86ExpandPseudo.cpp
lib/Target/X86/X86FixupBWInsts.cpp
lib/Target/X86/X86FixupLEAs.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrBuilder.h
lib/Target/X86/X86InstrInfo.cpp