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[SelectionDAG] Correct the early out in SelectionDAG::getZeroExtendInReg to work...
authorCraig Topper <craig.topper@intel.com>
Fri, 13 Oct 2017 00:18:58 +0000 (00:18 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 13 Oct 2017 00:18:58 +0000 (00:18 +0000)
commit862291753bb9abe31b2dabbf52be4f24b2890e1c
tree597a61c1d86459f1d2c4ea5721170f3fdf23d151tree | snapshot
parent5cb6ac0fdba390c29bb001d8b767e8155e35533ecommit | diff
[SelectionDAG] Correct the early out in SelectionDAG::getZeroExtendInReg to work properly for vector types.

I don't know if we ever hit this case or not. Turning it into an assert only fired on expanding some atomic operation in a SystemZ lit test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315648 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff | blob | history
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