]> granicus.if.org Git - llvm/commit
[MBP] Disable aggressive loop rotate in plain mode
authorGuozhi Wei <carrot@google.com>
Thu, 22 Aug 2019 16:21:32 +0000 (16:21 +0000)
committerGuozhi Wei <carrot@google.com>
Thu, 22 Aug 2019 16:21:32 +0000 (16:21 +0000)
commit83843cc07cc0c4ba31895cc9a0925096aa31c306
tree037f1f04f096d7e08c7865a8c7f317ba66237e09
parentf6826f8d24a3c304baa714a46078f647792fbeee
[MBP] Disable aggressive loop rotate in plain mode

Patch https://reviews.llvm.org/D43256 introduced more aggressive loop layout optimization which depends on profile information. If profile information is not available, the statically estimated profile information(generated by BranchProbabilityInfo.cpp) is used. If user program doesn't behave as BranchProbabilityInfo.cpp expected, the layout may be worse.

To be conservative this patch restores the original layout algorithm in plain mode. But user can still try the aggressive layout optimization with -force-precise-rotation-cost=true.

Differential Revision: https://reviews.llvm.org/D65673

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369664 91177308-0d34-0410-b5e6-96231b3b80d8
58 files changed:
lib/CodeGen/MachineBlockPlacement.cpp
test/CodeGen/AArch64/cmpxchg-idioms.ll
test/CodeGen/AArch64/tailmerging_in_mbp.ll
test/CodeGen/AMDGPU/collapse-endcf.ll
test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
test/CodeGen/AMDGPU/global_smrd_cfg.ll
test/CodeGen/AMDGPU/i1-copy-from-loop.ll
test/CodeGen/AMDGPU/indirect-addressing-si.ll
test/CodeGen/AMDGPU/loop_exit_with_xor.ll
test/CodeGen/AMDGPU/multilevel-break.ll
test/CodeGen/AMDGPU/optimize-negated-cond.ll
test/CodeGen/AMDGPU/si-annotate-cf.ll
test/CodeGen/AMDGPU/wave32.ll
test/CodeGen/AMDGPU/wqm.ll
test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
test/CodeGen/ARM/arm-and-tst-peephole.ll
test/CodeGen/ARM/atomic-cmp.ll
test/CodeGen/ARM/atomic-cmpxchg.ll
test/CodeGen/ARM/code-placement.ll
test/CodeGen/ARM/pr32578.ll
test/CodeGen/Hexagon/bug6757-endloop.ll
test/CodeGen/Hexagon/early-if-merge-loop.ll
test/CodeGen/Hexagon/prof-early-if.ll
test/CodeGen/Hexagon/redundant-branching2.ll
test/CodeGen/PowerPC/atomics-regression.ll
test/CodeGen/PowerPC/block-placement-1.mir
test/CodeGen/PowerPC/cmp_elimination.ll
test/CodeGen/PowerPC/licm-remat.ll
test/CodeGen/PowerPC/machine-pre.ll
test/CodeGen/RISCV/atomic-rmw.ll
test/CodeGen/RISCV/remat.ll
test/CodeGen/Thumb/consthoist-physical-addr.ll
test/CodeGen/Thumb/pr42760.ll
test/CodeGen/X86/block-placement.ll
test/CodeGen/X86/code_placement.ll
test/CodeGen/X86/code_placement_ignore_succ_in_inner_loop.ll
test/CodeGen/X86/code_placement_no_header_change.ll
test/CodeGen/X86/conditional-tailcall.ll
test/CodeGen/X86/loop-blocks.ll
test/CodeGen/X86/loop-rotate.ll [deleted file]
test/CodeGen/X86/lsr-loop-exit-cond.ll
test/CodeGen/X86/move_latch_to_loop_top.ll
test/CodeGen/X86/pr38185.ll
test/CodeGen/X86/ragreedy-hoist-spill.ll
test/CodeGen/X86/reverse_branches.ll
test/CodeGen/X86/speculative-load-hardening.ll
test/CodeGen/X86/tail-dup-merge-loop-headers.ll
test/CodeGen/X86/tail-dup-repeat.ll
test/CodeGen/X86/vector-shift-by-select-loop.ll
test/CodeGen/X86/widen_arith-1.ll
test/CodeGen/X86/widen_arith-2.ll
test/CodeGen/X86/widen_arith-3.ll
test/CodeGen/X86/widen_arith-4.ll
test/CodeGen/X86/widen_arith-5.ll
test/CodeGen/X86/widen_arith-6.ll
test/CodeGen/X86/widen_cast-4.ll
test/DebugInfo/X86/PR37234.ll
test/DebugInfo/X86/dbg-value-transfer-order.ll