* x86id.re (yasm_x86__parse_insn): Add checking of effective address size.

* x86id.re (yasm_x86__parse_insn): Add checking of effective address size.

* x86arch.h (x86_new_insn_data): Add shortmov_op for shortmov post-action.
* x86bc.c (x86_insn): Likewise.
(yasm_x86__bc_create_insn): Copy shortmov_op to instruction.
(x86_bc_insn_resolve): Handle shortmov_op post-action.
* x86id.re (yasm_x86__parse_insn): Set shortmov_op post-action if desired.

* x86id.re (mov_insn): Through reorder and use of new shortmov_op
post-action, change generated code for mov on AMD64.  On AMD64, the short
mov (opcode A0/A1/A2/A3), generated when moving to AL/AX/EAX/RAX from an
absolute address (no registers) has a 64-bit size in 64-bit mode.  While an
address override can reduce it to 32-bits, automatically generating such an
override does not fit well with the model of not doing anything behind the
programmer's back.  Instead, we now generate the 32-bit address size MOD/RM
form unless the address size is specifically set to 64 bits using [qword 0]
notation (this is the equivalent of the GNU AS movabs pseudo-instruction).
The short mov is still generated in 32-bit mode, whether obtained via BITS
setting or an a32 prefix in BITS 64 mode.  (The a32 prefix handling
necessitated the new shortmov post-action.)  Examples (pulled from new
mem64.asm):

    mov ax, [0]                         ; 66 8B 04 25 00 00 00 00
    mov rax, [dword 0]                  ; 48 8B 04 25 00 00 00 00
    mov al, [qword 0xfedcba9876543210]  ; A0 10 32 54 76 98 BA DC FE
    mov al, [0xfedcba9876543210]        ; 8A 04 25 10 32 54 76 (+ warning)
    a32 mov rax, [0]                    ; 67 48 A1 00 00 00 00

* mem64.asm: Update test to match code changes.
* mem64.hex: Likewise.
* mem64.errwarn: Likewise.

Related to: Bugzilla Bug 33
            Reported by: Jeff Lawson <jlawson-yasm@bovine.net>

svn path=/trunk/yasm/; revision=1134