]> granicus.if.org Git - llvm/commit
[AVX-512] Teach two address instruction pass to replace masked move instructions...
authorCraig Topper <craig.topper@gmail.com>
Sat, 14 Jan 2017 07:50:52 +0000 (07:50 +0000)
committerCraig Topper <craig.topper@gmail.com>
Sat, 14 Jan 2017 07:50:52 +0000 (07:50 +0000)
commit7b47370e8e993342c5b91139d7679b59c989132e
treea64afb7cf997d00b8ee2417aec8dda65ef2d5d7d
parent49a15c1e8e517efa7bdb33bab849b49a3dac290e
[AVX-512] Teach two address instruction pass to replace masked move instructions with blendm instructions when its beneficial.

Isel now selects masked move instructions for vselect instead of blendm. But sometimes it beneficial to register allocation to remove the tied register constraint by using blendm instructions.

This also picks up cases where the masked move was created due to a masked load intrinsic.

Differential Revision: https://reviews.llvm.org/D28454

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292005 91177308-0d34-0410-b5e6-96231b3b80d8
16 files changed:
lib/Target/X86/X86InstrAVX512.td
lib/Target/X86/X86InstrInfo.cpp
test/CodeGen/X86/avx512-bugfix-26264.ll
test/CodeGen/X86/avx512-masked-memop-64-32.ll
test/CodeGen/X86/avx512-masked_memop-16-8.ll
test/CodeGen/X86/avx512-regcall-NoMask.ll
test/CodeGen/X86/avx512-vec-cmp.ll
test/CodeGen/X86/avx512bw-vec-cmp.ll
test/CodeGen/X86/avx512bwvl-vec-cmp.ll
test/CodeGen/X86/avx512vl-vec-cmp.ll
test/CodeGen/X86/masked_memop.ll
test/CodeGen/X86/vector-shuffle-128-v16.ll
test/CodeGen/X86/vector-shuffle-256-v16.ll
test/CodeGen/X86/vector-shuffle-256-v32.ll
test/CodeGen/X86/vector-shuffle-512-v16.ll
test/CodeGen/X86/vector-shuffle-masked.ll