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(parent: 2c47ef0) | patch
AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Sat, 29 Jun 2019 00:33:13 +0000 (00:33 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Sat, 29 Jun 2019 00:33:13 +0000 (00:33 +0000)
commit7846e1a4c86ed67c375e63af995b801f2d970068
treea8922010c97f8669fcfe36616929691405b06c33tree | snapshot
parent2c47ef085809710637d21fc076195bb2edf65079commit | diff
AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364698 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp diff | blob | history
test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir [new file with mode: 0644] blob
test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir [new file with mode: 0644] blob
test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir [new file with mode: 0644] blob
test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.fmax.mir [new file with mode: 0644] blob
test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.fmin.mir [new file with mode: 0644] blob
test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir [new file with mode: 0644] blob
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