]> granicus.if.org Git - llvm/commit
[AArch64][SVE] Add SPLAT_VECTOR ISD Node
authorGraham Hunter <graham.hunter@arm.com>
Fri, 18 Oct 2019 11:48:35 +0000 (11:48 +0000)
committerGraham Hunter <graham.hunter@arm.com>
Fri, 18 Oct 2019 11:48:35 +0000 (11:48 +0000)
commit77a2562985b102cb6eec1c78d832f37922dde712
tree701663ba1148a9b64a203b1e9d8b12adead973e3
parent7944d32db7f691540b7a3aaccd159963692c2626
[AArch64][SVE] Add SPLAT_VECTOR ISD Node

Adds a new ISD node to replicate a scalar value across all elements of
a vector. This is needed for scalable vectors, since BUILD_VECTOR cannot
be used.

Fixes up default type legalization for scalable vectors after the
new MVT type ranges were introduced.

At present I only use this node for scalable vectors. A DAGCombine has
been added to transform a BUILD_VECTOR into a SPLAT_VECTOR if all
elements are the same, but only if the default operation action of
Expand has been overridden by the target.

I've only added result promotion legalization for scalable vector
i8/i16/i32/i64 types in AArch64 for now.

Reviewers: t.p.northover, javed.absar, greened, cameron.mcinally, jmolloy

Reviewed By: jmolloy

Differential Revision: https://reviews.llvm.org/D47775

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375222 91177308-0d34-0410-b5e6-96231b3b80d8
13 files changed:
include/llvm/CodeGen/ISDOpcodes.h
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
lib/CodeGen/SelectionDAG/LegalizeTypes.h
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
lib/CodeGen/TargetLoweringBase.cpp
lib/Target/AArch64/AArch64ISelLowering.cpp
lib/Target/AArch64/AArch64ISelLowering.h
lib/Target/AArch64/AArch64SVEInstrInfo.td
lib/Target/AArch64/SVEInstrFormats.td
test/CodeGen/AArch64/sve-vector-splat.ll [new file with mode: 0644]