]> granicus.if.org Git - llvm/commit
[AMDGPU] Added v5i32 and v5f32 register classes
authorTim Renouf <tpr.llvm@botech.co.uk>
Fri, 22 Mar 2019 10:11:21 +0000 (10:11 +0000)
committerTim Renouf <tpr.llvm@botech.co.uk>
Fri, 22 Mar 2019 10:11:21 +0000 (10:11 +0000)
commit7684aab92af11ee8bc1a3239ac6bde5c0c110ef6
tree39046b821b16b6c5d8ed8ff0e7ae1961a00f3499
parentaa5b4e00ae035b5e4ef55a295b5760e04a71fc16
[AMDGPU] Added v5i32 and v5f32 register classes

They are not used by anything yet, but a subsequent commit will start
using them for image ops that return 5 dwords.

Differential Revision: https://reviews.llvm.org/D58903

Change-Id: I63e1904081e39a6d66e4eb96d51df25ad399d271

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356735 91177308-0d34-0410-b5e6-96231b3b80d8
12 files changed:
lib/Target/AMDGPU/AMDGPUCallingConv.td
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
lib/Target/AMDGPU/SIISelLowering.cpp
lib/Target/AMDGPU/SIInstrInfo.cpp
lib/Target/AMDGPU/SIInstructions.td
lib/Target/AMDGPU/SIRegisterInfo.cpp
lib/Target/AMDGPU/SIRegisterInfo.td
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
test/CodeGen/AMDGPU/select-vectors.ll
test/CodeGen/AMDGPU/spill-wide-sgpr.ll