]> granicus.if.org Git - llvm/commit
AMDGPU: Move MnemonicAlias out of instruction def hierarchy
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 9 Sep 2019 17:25:35 +0000 (17:25 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 9 Sep 2019 17:25:35 +0000 (17:25 +0000)
commit6d3a2c9e60de135a74bd91285a8f2ce212b0648a
tree3dadc40bc9833bde30632349d258781662c7b3cd
parent17eef45fa870b7cbb4a3c9f3dd7aac63b55682ce
AMDGPU: Move MnemonicAlias out of instruction def hierarchy

Unfortunately MnemonicAlias defines a "Predicates" field just like an
instruction or pattern, with a somewhat different interpretation.

This ends up overriding the intended Predicates set by
PredicateControl on the pseudoinstruction defintions with an empty
list. This allowed incorrectly selecting instructions that should have
been rejected due to the SubtargetPredicate from patterns on the
instruction definition.

This does remove the divergent predicate from the 64-bit shift
patterns, which were already not used for the 32-bit shift, so I'm not
sure what the point was. This also removes a second, redundant copy of
the 64-bit divergent patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371427 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/VOP1Instructions.td
lib/Target/AMDGPU/VOP2Instructions.td
lib/Target/AMDGPU/VOP3Instructions.td
lib/Target/AMDGPU/VOPInstructions.td
test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir