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(parent: f6c436e) | patch
R600/SI: Fix spilling of m0 register
authorTom Stellard <thomas.stellard@amd.com>
Fri, 14 Nov 2014 20:43:26 +0000 (20:43 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Fri, 14 Nov 2014 20:43:26 +0000 (20:43 +0000)
commit6beb81daa5539761af6170c9993b678e0497ed76
tree8e59b9451f304045d9248465865544ee8bb76ffbtree | snapshot
parentf6c436e9d712ced3973ada3e6e8048cb11ed631acommit | diff
R600/SI: Fix spilling of m0 register

If we have spilled the value of the m0 register, then we need to restore
it with v_readlane_b32 to a regular sgpr, because v_readlane_b32 can't
write to m0.

v_readlane_b32 can't write to m0, so

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222036 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/R600/SIRegisterInfo.cpp diff | blob | history
test/CodeGen/R600/m0-spill.ll [new file with mode: 0644] blob
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