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AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 24 Jun 2019 17:54:12 +0000 (17:54 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 24 Jun 2019 17:54:12 +0000 (17:54 +0000)
commit6ba4049f7df67cba95ea93740e41f3b500d5949a
tree21167e9eee384002f8fa1006ae745c5a14861eaftree | snapshot
parent1432e6009cd42a06ee5e1423de127f05e32edc6ccommit | diff
AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect

Scalar extends to s64 can use S_BFE_{I64|U64}, but vector extends need
to extend to the 32-bit half, and then to 64.

I'm not sure what the line should be between what RegBankSelect
handles, and what instruction select does, but for now I'm erring on
the side of RegBankSelect for future post-RBS combines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364212 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp diff | blob | history
test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir diff | blob | history
test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir diff | blob | history
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