]> granicus.if.org Git - llvm/commit
[PowerPC] Implement BE VSX load/store builtins - llvm portion.
authorTony Jiang <jtony@ca.ibm.com>
Tue, 15 Nov 2016 14:25:56 +0000 (14:25 +0000)
committerTony Jiang <jtony@ca.ibm.com>
Tue, 15 Nov 2016 14:25:56 +0000 (14:25 +0000)
commit6ad6c513ee5746840b4183c93faae89cafd5dacb
tree4bef501f47de1ef3621e67a6e3298b60ff2db04e
parent6ee545953fcfba8bb7dd0ef3abc01ca7c7d4e4f7
[PowerPC] Implement BE VSX load/store builtins - llvm portion.

This patch implements all the overloads for vec_xl_be and vec_xst_be. On BE,
they behaves exactly the same with vec_xl and vec_xst, therefore they are
simply implemented by defining a matching macro. On LE, they are implemented
by defining new builtins and intrinsics. For int/float/long long/double, it
is just a load (lxvw4x/lxvd2x) or store(stxvw4x/stxvd2x). For char/char/short,
we also need some extra shuffling before or after call the builtins to get the
desired BE order. For int128, simply call vec_xl or vec_xst.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286967 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/IR/IntrinsicsPowerPC.td
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/PowerPC/PPCInstrVSX.td
test/CodeGen/PowerPC/vsx.ll