]> granicus.if.org Git - llvm/commit
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX.
authorCraig Topper <craig.topper@intel.com>
Mon, 2 Sep 2019 20:16:30 +0000 (20:16 +0000)
committerCraig Topper <craig.topper@intel.com>
Mon, 2 Sep 2019 20:16:30 +0000 (20:16 +0000)
commit68fb334e9ebf8b6b9b1edb7b9e20d0bc32fe8bef
treeef4aeee1f6f08bc6bb0406dd150e5003714437f4
parent14dc68ac6b6233c44152e1e4ec88daeddccf43a4
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX.

FP128 values are passed in xmm registers so should be asssociated
with an SSE feature rather than MMX which uses a different set
of registers.

llc enables sse1 and sse2 by default with x86_64. But does not
enable mmx. Clang enables all 3 features by default.

I've tried to add command lines to test with -sse
where possible, but any test that returns a value in an xmm
register fails with a fatal error with -sse since we have no
defined ABI for that scenario.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370682 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/atomic-non-integer-fp128.ll [new file with mode: 0644]
test/CodeGen/X86/atomic-non-integer.ll
test/CodeGen/X86/atomicf128.ll
test/CodeGen/X86/extract-store.ll
test/CodeGen/X86/fp128-cast.ll
test/CodeGen/X86/fp128-select.ll
test/CodeGen/X86/vec_fp_to_int.ll