Merging r352607 r352608 r353015 r353061 r353138 r353141 r353334 r353489

Merging r352607 r352608 r353015 r353061 r353138 r353141 r353334 r353489

And re-generate expectations for a test:
$ utils/update_llc_test_checks.py --llc-binary ../build.release/bin/llc test/CodeGen/X86/x87-schedule.ll

Will also merge cfe r353142 for a clang-side test.

This merge was requested in PR40667.

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r352607 | ctopper | 2019-01-30 08:08:44 +0100 (Wed, 30 Jan 2019) | 1 line

[X86] Add FPSW as a Def on some FP instructions that were missing it.
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r352608 | ctopper | 2019-01-30 08:33:24 +0100 (Wed, 30 Jan 2019) | 5 lines

[X86] Remove a couple places where we unnecessarily pass 0 to the EmitPriority of some FP instruction aliases. NFC

As far as I can tell we already won't emit these aliases due to an operand count check in the tablegen code. Removing these because I couldn't make sense of the inconsistency between fadd and fmul from reading the code.

I checked the AsmMatcher and AsmWriter files before and after this change and there were no differences.
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r353015 | ctopper | 2019-02-04 05:15:10 +0100 (Mon, 04 Feb 2019) | 3 lines

[X86] Print %st(0) as %st when its implicit to the instruction. Continue printing it as %st(0) when its encoded in the instruction.

This is a step back from the change I made in r352985. This appears to be more consistent with gcc and objdump behavior.
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r353061 | ctopper | 2019-02-04 18:28:18 +0100 (Mon, 04 Feb 2019) | 5 lines

[X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two arguments where on is %st.

All of these instructions consume one encoded register and the other register is %st. They either write the result to %st or the encoded register. Previously we printed both arguments when the encoded register was written. And we printed one argument when the result was written to %st. For the stack popping forms the encoded register is always the destination and we didn't print both operands. This was inconsistent with gcc and objdump and just makes the output assembly code harder to read.

This patch changes things to always print both operands making us consistent with gcc and objdump. The parser should still be able to handle the single register forms just as it did before. This also matches the GNU assembler behavior.
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r353138 | ctopper | 2019-02-05 05:48:23 +0100 (Tue, 05 Feb 2019) | 1 line

[X86] Add test case from PR40529. NFC
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r353141 | ctopper | 2019-02-05 07:13:06 +0100 (Tue, 05 Feb 2019) | 16 lines

[X86] Connect the default fpsr and dirflag clobbers in inline assembly to the registers we have defined for them.

Summary:
We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly.

This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that.

Reviewers: rnk

Reviewed By: rnk

Subscribers: eraman, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D57641
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r353334 | ctopper | 2019-02-06 20:50:59 +0100 (Wed, 06 Feb 2019) | 1 line

[X86] Change the CPU on the test case for pr40529.ll to really show the bug. NFC
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r353489 | ctopper | 2019-02-08 01:44:39 +0100 (Fri, 08 Feb 2019) | 14 lines

[X86] Add FPCW as a register and start using it as an implicit use on floating point instructions.

Summary:
FPCW contains the rounding mode control which we manipulate to implement fp to integer conversion by changing the roudning mode, storing the value to the stack, and then changing the rounding mode back. Because we didn't model FPCW and its dependency chain, other instructions could be scheduled into the middle of the sequence.

This patch introduces the register and adds it as an implciit def of FLDCW and implicit use of the FP binary arithmetic instructions and store instructions. There are more instructions that need to be updated, but this is a good start. I believe this fixes at least the reduced test case from PR40529.

Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor

Subscribers: dim, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D57735
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_80@353818 91177308-0d34-0410-b5e6-96231b3b80d8