]> granicus.if.org Git - clang/commit
Merging r366480:
authorHans Wennborg <hans@hanshq.net>
Fri, 19 Jul 2019 09:43:12 +0000 (09:43 +0000)
committerHans Wennborg <hans@hanshq.net>
Fri, 19 Jul 2019 09:43:12 +0000 (09:43 +0000)
commit65b03841891d5887eefbf4dddb5ef4ea4091c47f
tree5129067b574c77ef2ccd7219244cdd43ba17fee5
parent4d7befb986edbbc419f1ecac76b8b998e0ff0b58
Merging r366480:
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r366480 | asb | 2019-07-18 20:29:59 +0200 (Thu, 18 Jul 2019) | 25 lines

[RISCV] Hard float ABI support

The RISC-V hard float calling convention requires the frontend to:

* Detect cases where, once "flattened", a struct can be passed using
int+fp or fp+fp registers under the hard float ABI and coerce to the
appropriate type(s)
* Track usage of GPRs and FPRs in order to gate the above, and to
determine when signext/zeroext attributes must be added to integer
scalars

This patch attempts to do this in compliance with the documented ABI,
and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as
author of that code I've tagged you as reviewer for initial feedback on
my usage.

Note that a previous version of the ABI indicated that when passing an
int+fp struct using a GPR+FPR, the int would need to be sign or
zero-extended appropriately. GCC never did this and the ABI was changed,
which makes life easier as ABIArgInfo::CoerceAndExpand can't currently
handle sign/zero-extension attributes.

Re-landed after backing out 366450 due to missed hunks.

Differential Revision: https://reviews.llvm.org/D60456
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git-svn-id: https://llvm.org/svn/llvm-project/cfe/branches/release_90@366554 91177308-0d34-0410-b5e6-96231b3b80d8
14 files changed:
lib/Basic/Targets/RISCV.cpp
lib/Basic/Targets/RISCV.h
lib/CodeGen/TargetInfo.cpp
test/CodeGen/riscv32-ilp32-ilp32f-abi.c
test/CodeGen/riscv32-ilp32-ilp32f-ilp32d-abi.c
test/CodeGen/riscv32-ilp32d-abi.c [new file with mode: 0644]
test/CodeGen/riscv32-ilp32f-abi.c [new file with mode: 0644]
test/CodeGen/riscv32-ilp32f-ilp32d-abi.c [new file with mode: 0644]
test/CodeGen/riscv64-lp64-lp64f-abi.c
test/CodeGen/riscv64-lp64-lp64f-lp64d-abi.c
test/CodeGen/riscv64-lp64d-abi.c [new file with mode: 0644]
test/CodeGen/riscv64-lp64f-lp64d-abi.c [new file with mode: 0644]
test/Driver/riscv-abi.c
test/Preprocessor/riscv-target-features.c