]> granicus.if.org Git - llvm/commit
[X86] Explcitly disable VEXTRACT instruction matching for an immediate of 0. Remove...
authorCraig Topper <craig.topper@intel.com>
Wed, 22 May 2019 21:00:18 +0000 (21:00 +0000)
committerCraig Topper <craig.topper@intel.com>
Wed, 22 May 2019 21:00:18 +0000 (21:00 +0000)
commit64e37aff5f40e23e85c792bc6f500b923a0ed034
treebecc79de590b8fbbb7bc527a6ea6d1b519543186
parent35e2e8d045c441f64fefbfd219b9d30ec7ed3cb6
[X86] Explcitly disable VEXTRACT instruction matching for an immediate of 0. Remove a bunch of isel patterns that become unnecessary.

We effectively had a second set of isel patterns that tried to use a
regular store instruction and an extract_subreg instruction. Or a masked move
and an extract_subreg. These patterns were intended to override the
matching of VEXTRACT instructions by taking advantage of the priority
of the explicit immediate 0 for the index.

This patch instaed just disables the immediate 0 matchin the VEXTRACT
patterns. This each of the component pieces of the larger patterns will
match by themselves.

This found a bug of sorts were we didn't use 128-bit store for 512->128
extract on KNL. Its unclear what the right thing here should be.
Using the vextract avoids constraining the register allocator to use
xmm0-15. But it always results in a longer encoding if the register
allocator ends up choosing xmm0-15 anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361431 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86InstrAVX512.td
lib/Target/X86/X86InstrFragmentsSIMD.td
lib/Target/X86/X86InstrVecCompiler.td
test/CodeGen/X86/avx512-insert-extract.ll