]> granicus.if.org Git - llvm/commit
projects / llvm / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 4eeab93) | patch
[ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode
authorAndre Vieira <andre.simoesdiasvieira@arm.com>
Wed, 18 Oct 2017 14:47:37 +0000 (14:47 +0000)
committerAndre Vieira <andre.simoesdiasvieira@arm.com>
Wed, 18 Oct 2017 14:47:37 +0000 (14:47 +0000)
commit63400097f6799a12e7aa3e58db0499e6c338619b
treee84703897ff899702ac035b8c11c503fac56419ftree | snapshot
parent4eeab93a12331c8856a0fd188ce20cf0f79b2eadcommit | diff
[ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode

Differential Revision: https://reviews.llvm.org/D38347

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316085 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/Disassembler/ARMDisassembler.cpp diff | blob | history
test/MC/Disassembler/ARM/arm-vmrs_vmsr.txt diff | blob | history
test/MC/Disassembler/ARM/thumb-vmrs_vmsr.txt diff | blob | history
Unnamed repository; edit this file 'description' to name the repository.