]> granicus.if.org Git - llvm/commit
[X86] Add a VBROADCAST_LOAD ISD opcode representing a scalar load broadcasted to...
authorCraig Topper <craig.topper@intel.com>
Tue, 1 Oct 2019 16:28:20 +0000 (16:28 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 1 Oct 2019 16:28:20 +0000 (16:28 +0000)
commit61fe4ef60e3668bf148382478f6a8039e55622a0
tree26c5cdacc8952b9c4ccfa1a8d06da05478503f20
parent303c51ac6328e8aa221d03f58398f6681351e356
[X86] Add a VBROADCAST_LOAD ISD opcode representing a scalar load broadcasted to a vector.

Summary:
This adds the ISD opcode and a DAG combine to create it. There are
probably some places where we can directly create it, but I'll
leave that for future work.

This updates all of the isel patterns to look for this new node.
I had to add a few additional isel patterns for aligned extloads
which we should probably fix with a DAG combine or something. This
does mean that the broadcast load folding for avx512 can no
longer match a broadcasted aligned extload.

There's still some work to do here for combining a broadcast of
a broadcast_load. We also need to improve extractelement or
demanded vector elements of a broadcast_load. I'll try to get
those done before I submit this patch.

Reviewers: RKSimon, spatel

Reviewed By: RKSimon

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68198

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373349 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelDAGToDAG.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86ISelLowering.h
lib/Target/X86/X86InstrAVX512.td
lib/Target/X86/X86InstrFragmentsSIMD.td
lib/Target/X86/X86InstrSSE.td
test/CodeGen/X86/avx512-intrinsics-upgrade.ll
test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll