AMDGPU: Workaround for instruction size with literals

AMDGPU: Workaround for instruction size with literals

Instructions with a 32-bit base encoding with an optional
32-bit literal encoded after them report their size as 4
for the disassembler. Consider these when computing the
MachineInstr size. This fixes problems caused by size estimate
consistency in BranchRelaxation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285743 91177308-0d34-0410-b5e6-96231b3b80d8