]> granicus.if.org Git - llvm/commit
[X86] Add FPCW as a register and start using it as an implicit use on floating point...
authorCraig Topper <craig.topper@intel.com>
Fri, 8 Feb 2019 00:44:39 +0000 (00:44 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 8 Feb 2019 00:44:39 +0000 (00:44 +0000)
commit5e75b645f6ee7218d38977762a5fdff148708f7b
tree1d159cb9c36c909a1b52899f1c1c2bc9bd6fcccc
parent218a20ac21ce7fbdb07f2680f26c0703659fc5f1
[X86] Add FPCW as a register and start using it as an implicit use on floating point instructions.

Summary:
FPCW contains the rounding mode control which we manipulate to implement fp to integer conversion by changing the roudning mode, storing the value to the stack, and then changing the rounding mode back. Because we didn't model FPCW and its dependency chain, other instructions could be scheduled into the middle of the sequence.

This patch introduces the register and adds it as an implciit def of FLDCW and implicit use of the FP binary arithmetic instructions and store instructions. There are more instructions that need to be updated, but this is a good start. I believe this fixes at least the reduced test case from PR40529.

Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor

Subscribers: dim, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D57735

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353489 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86InstrFPStack.td
lib/Target/X86/X86RegisterInfo.cpp
lib/Target/X86/X86RegisterInfo.td
test/CodeGen/MIR/X86/memory-operands.mir
test/CodeGen/X86/ipra-reg-usage.ll
test/CodeGen/X86/pr34080.ll
test/CodeGen/X86/pr40529.ll