]> granicus.if.org Git - llvm/commit
[AArch64][GlobalISel] Select arithmetic extended register patterns
authorJessica Paquette <jpaquette@apple.com>
Thu, 29 Aug 2019 21:53:58 +0000 (21:53 +0000)
committerJessica Paquette <jpaquette@apple.com>
Thu, 29 Aug 2019 21:53:58 +0000 (21:53 +0000)
commit5d27af8ddc107cd5ce4ec04251f5c20fcd76a471
tree731b2bac68681e7e5066c928dd6912644825b66a
parent387681cec337c8dcaa89de088adf6e3b3aae8127
[AArch64][GlobalISel] Select arithmetic extended register patterns

This teaches GISel to select patterns which fold an extend plus optional shift
into the addressing mode. In particular, adds and subs.

Factor out the arith extended register ComplexPatterns in AArch64InstrFormats.td
and create GISel equivalents.

Add some equivalent functions to the ones in AArch64ISelDAGToDAG:

- `selectArithExtendedRegister`
- `narrowExtendRegIfNeeded`
- `getExtendTypeForInst`

`getExtendTypeForInst` includes the checks for loads and stores. This will be
used for WRO addressing modes in loads + stores.

Teach selectCopy to properly handle subregister copies on the same bank in
order to support `narrowExtendRegIfNeeded`. The extended register must be a
GPR32, so we need to support same-bank subregister copies.

Fix a bug in getSubRegForClass which would cause registers on things like
GPR32common to end up getting ssub. Just change the check to look for FPR32
rather than GPR32.

For tests:

- Add select-arith-extended-reg.mir
- Update addsub_ext.ll to include GlobalISel checks

Differential Revision: https://reviews.llvm.org/D66835

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370410 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64InstrFormats.td
lib/Target/AArch64/AArch64InstrInfo.td
lib/Target/AArch64/AArch64InstructionSelector.cpp
test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir [new file with mode: 0644]
test/CodeGen/AArch64/addsub_ext.ll