]> granicus.if.org Git - llvm/commit
DAGCombine: Combine BUILD_VECTOR to TRUNCATE
authorZvi Rackover <zvi.rackover@intel.com>
Mon, 3 Jul 2017 15:47:40 +0000 (15:47 +0000)
committerZvi Rackover <zvi.rackover@intel.com>
Mon, 3 Jul 2017 15:47:40 +0000 (15:47 +0000)
commit5c26a9c9de337848d43de1c78aa3255ffc8b5896
treed250b7d8ce0e8a71acf5dc7af6d06ee6a7530734
parent40f3703b3669ff78df4d7cdb1d2ad741ab9addb5
DAGCombine: Combine BUILD_VECTOR to TRUNCATE

Summary:
Add a combine for creating a truncate to replace a build_vector composed of extracts with
indices that form a stride-2^N series.

Example:
v8i32 V = ...

v4i32 build_vector((extract_elt V, 0), (extract_elt V, 2), (extract_elt V, 4), (extract_elt V, 6))
-->
v4i32 truncate (bitcast V to v4i64)

Related discussion in llvm-dev about canonicalizing shuffles to
truncates in LLVM IR:
http://lists.llvm.org/pipermail/llvm-dev/2017-January/108936.html.

Reviewers: spatel, RKSimon, efriedma, igorb, craig.topper, wolfgangp, delena

Reviewed By: delena

Subscribers: guyblank, delena, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D34077

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307036 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/Target/TargetLowering.h
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
lib/Target/X86/X86ISelLowering.h
test/CodeGen/X86/shuffle-vs-trunc-256.ll
test/CodeGen/X86/shuffle-vs-trunc-512.ll
test/CodeGen/X86/vector-truncate-combine.ll